1. Field of the Invention
The present invention relates to a wide dynamic range bilinear multiplier and more particularly, to a bilinear multiplier or mixer configured in an improved Gilbert topology which provides an increased linear range relative to known Gilbert mixers which obviates the need for an additional predistortion stage without sacrificing the phase or broadband performance properties of the mixer.
2. Description of the Prior Art
Mixers are used in various applications, such as frequency conversion and bilinear signal multiplication applications. Many known RF systems typically use mixers for RF receiver applications for upconverting and downconverting the RF signals. In such applications, an oscillator is used to provide a local oscillator (LO) source frequency that is amplified by an LO buffer amplifier to a signal level large enough to switch diodes or transistors in the mixer. A relatively small level RF signal is applied to the other input of the mixer to be frequency converted. The output of the mixer is the difference and sum of the frequencies of the input signals. In such an application, the LO port is driven into saturation where the noise figure, conversion gain and IP3 typically improve with a larger LO drive level.
Mixers are also known to be used in another application in order to modulate a digital data stream of 1's and 0's onto a carrier frequency. In this application, the LO port is driven non-linearly. In both cases discussed above, a linear relationship is not required between the output and both of the inputs to the mixer. However, there are applications in which both input ports to the mixer need to be linearly related to the output port, such as in variable amplitude and phase (VAP) control circuits, which typically use a Gilbert cell mixer. Such applications are typically used for higher order modulation schemes, such as OPSK and 16 QAM applications and typically require increasing the linear input power range of the LO port of the mixer using circuit modifications to the basic mixer cell. However, for many mixers, especially active mixer topologies, such as the Gilbert cell, it is relatively complicated to increase the linear range of the device.
A typical Gilbert cell is illustrated in FIG. 1A. The mixer is named after its inventor and is described in detail in "DESIGN CONSIDERATIONS FOR BJT ACTIVE MIXERS", by Barrie Gilbert, Workshop Notes, Analog Devices, Inc., Rev. 2.2, Sep. 4, 1994 and U.S. Pat. No. 5,589,791, hereby incorporated by reference. Such Gilbert cell mixers include four transistors Q1, Q2, Q3, Q4 (FIG. 1) known as an upper quad core of transistors, Q1, Q2, Q3 and Q4. The upper quad core of transistors Q1, Q2, Q3 and Q4 are differentially connected in a common emitter configuration and in turn connected to a differentially connected pair of transistors Q5 and Q6. As shown in FIG. 1, the Gilbert cell mixer has two input ports RF.sub.in1, RF.sub.in2 and one output port OUTPUT.
In operation, when a DC voltage is applied to the input port RF.sub.in1, a hyperbolic tangent (tanh) function exists between the input port RF.sub.in2 and the output port OUTPUT as generally shown in FIG. 1B due to the linear transconductance of the transistors Q5 and Q6 for that range. However, the transconductance G.sub.m of transistors Q5 and Q6 becomes increasingly non-linear outside of the linear operating range as shown in FIG. 1B.
Various techniques are known for linearizing the output range of the transistors of Q5 and Q6. For example, as shown in FIG. 1, an emitter degeneration resistor R.sub.ee is connected between the emitter terminals of the transistors Q5 and Q6 for linearizing the RF input RF.sub.in2. In addition, other techniques, such as replacing the emitter degeneration resistor R.sub.ee by a near noiseless lossless spiral inductor are also known to be used for achieving high linearity without incurring a thermal noise degradation accompanied by the emitter degeneration resistor. Other techniques for linearizing the transistors Q5 and Q6 are also disclosed in U.S. Pat. No. 5,558,791 and "DESIGN CONSIDERATIONS FOR BJT ACTIVE MIXERS", supra.
One problem with such so called Gilbert mixers, is the need to linearize the upper quad core of transistors Q1, Q2, Q3 and Q4. In order to linearize the upper quad core of transistors Q1, Q2, Q3 and Q4 without incurring excessive bandwidth or noise performance penalties, a conventional diode predistortion circuit, such as illustrated in FIG. 2, is normally utilized. Unfortunately, the diode distortion circuit requires additional DC power, as well as semiconductor real estate and adds thermal noise as generally discussed in "ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS," by Paul R. Gray and Robert G. Meyer, Second Edition, John Wiley & Sons, New York, 1984.
Emitter degeneration circuitry is typically not used on the upper transistor quad core Q1, Q2, Q3, Q4 because of the added thermal noise, as well as the degradation in bandwidth due to the higher impedance applied to the collectors of the transistors Q5 and Q6 which causes a higher degree of the Miller effect on the bottom transistors Q5 and Q6. In addition, emitter degradation circuitry results in the loss of voltage headroom and can substantially cause unwanted peaking in the upper quad core of transistors Q1, Q2, Q3 and Q4, which can result in dynamic phase distortion.
U.S. Pat. No. 5,331,086 discloses a linearization technique for the upper quad core of transistors Q1, Q2, Q3 and Q4 of a conventional Gilbert mixer. As disclosed in the '086 patent, the mixer includes common base configured transistors whose terminals are either grounded or connected to a constant voltage source. In particular, the common base transistors are essentially connected between the upper quad transistor core and the transistors Q5 and Q6. With such configuration, a relatively higher voltage supply is required for proper operation.
It is an object of the present invention to solve various problems in the prior art.
It is yet another object of the present invention to provide an improved Gilbert cell mixer which provides an increased linear range.
It is a further object of the present invention to provide an improved Gilbert cell mixer which provides an increased linear range without the need for additional diode predistortion circuitry.
It is yet a father object of the present invention to provide a improved Gilbert cell mixer which provides an increased linear range while allowing for a relatively low supply voltage.
Briefly, the present invention relates to a wide dynamic range bilinear multiplier implemented with an improved Gilbert cell mixer topology which linearizies the top quad core of transistors Q1, Q2, Q3 and Q4 to provide a true bilinear multiplier whose output is linearly related to both inputs over a relatively substantial input power range without the need for an additional diode predistortion circuit or increased voltage. In order to improve the linearity of the upper quad core of transistors Q1, Q2, Q3 and Q4, these transistors Q1, Q2, Q3 and Q4 are implemented as either multi-tanh doublets or multi-tanh triplets. Each multi-tanh doublet includes two pair of common emitter configured transistors Q.sub.xe and Q.sub.xae. The linear input voltage range of the multi-tanh doublets is maximized by proper selection of the emitter areas Q.sub.xae relative to Q.sub.xe, where Ae is an area factor greater than 1. Each of the multi-tanh doublets is connected to a mirror current driver, formed from a pair of common emitter connected transistors, which act as current sinks for each of the multi-tanh doublets. In an alternate embodiment of the invention, the upper transistor quad core transistors, Q1, Q2, Q3 and Q4 are formed from two multi-tanh triplets. An additional transistor is added to each of the multi-tanh doublets to form the multi-tanh triplets. In addition, another transistor is added to each of the mirror current driver circuits for each of the multi-tanh triplets. The use of the multi-tanh doublets and multi-tanh triplets allow the linear range of the upper quad transistor core transistors Q1, Q2, Q3 and Q4 to extended without the use of additional diode predistortion circuits or other performance penalties.